Negative Bias Temperature Instability in CMOS Devices

This paper reviews the experimental and modeling efforts to understand the mechanism of Negative Bias Temperature Instability (NBTI) in p-MOSFETs, which is becoming a serious reliability concern for analog and digital CMOS circuits. Conditions for interface and bulk trap generation and their dependence on stress voltage and oxide field, temperature and time are discussed. The role of inversion layer holes, hot-holes and hot-electrons are also discussed. The recovery of generated damage and its bias, temperature and AC frequency dependence are discussed. The degradation and recovery is modeled using the standard Reaction-Diffusion theory, and some unique data scaling features are pointed out. The impact of gate-oxide nitridation is also reviewed.